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<a name="details" id="details"></a><h2 class="groupheader">Overview</h2>
<div class="textblock"><p>This header file contains identifiers and register-level core functions (or macros) that can be used to access the Xilinx VoIP Decapsulator core. </p>
<p>For more information about the operation of this core see the hardware specification and documentation in the higher level driver <a class="el" href="xdecap_8h.html" title="This is the main header file for VoIP Decapsulator core. ">xdecap.h</a> file.</p>
<pre>
MODIFICATION HISTORY:</pre><pre>Ver   Who    Date     Changes
<hr/>

1.00   mmo   02/12/16 Initial release.</pre><pre></pre> </div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:ab90ba5ed847113b4cdfa527ae8f9d22a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdecap__hw_8h.html#ab90ba5ed847113b4cdfa527ae8f9d22a">XDecap_HW_H_</a></td></tr>
<tr class="memdesc:ab90ba5ed847113b4cdfa527ae8f9d22a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prevent circular inclusions by using protection macros.  <a href="#ab90ba5ed847113b4cdfa527ae8f9d22a">More...</a><br /></td></tr>
<tr class="separator:ab90ba5ed847113b4cdfa527ae8f9d22a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Register access macro definition</div></td></tr>
<tr class="memitem:a03b582a71ef5398000b744c91fe4890f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdecap__hw_8h.html#a03b582a71ef5398000b744c91fe4890f">XDecap_In32</a>&#160;&#160;&#160;Xil_In32</td></tr>
<tr class="memdesc:a03b582a71ef5398000b744c91fe4890f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Input Operations.  <a href="#a03b582a71ef5398000b744c91fe4890f">More...</a><br /></td></tr>
<tr class="separator:a03b582a71ef5398000b744c91fe4890f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a351361dd041772e13059c23711f9bf8c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdecap__hw_8h.html#a351361dd041772e13059c23711f9bf8c">XDecap_Out32</a>&#160;&#160;&#160;Xil_Out32</td></tr>
<tr class="memdesc:a351361dd041772e13059c23711f9bf8c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output Operations.  <a href="#a351361dd041772e13059c23711f9bf8c">More...</a><br /></td></tr>
<tr class="separator:a351361dd041772e13059c23711f9bf8c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa76b2fa202760bb7127ce994598bb8d5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdecap__hw_8h.html#aa76b2fa202760bb7127ce994598bb8d5">XDecap_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;<a class="el" href="xdecap__hw_8h.html#a03b582a71ef5398000b744c91fe4890f">XDecap_In32</a>((BaseAddress) + ((u32)RegOffset))</td></tr>
<tr class="memdesc:aa76b2fa202760bb7127ce994598bb8d5"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro reads a value from a Decap register.  <a href="#aa76b2fa202760bb7127ce994598bb8d5">More...</a><br /></td></tr>
<tr class="separator:aa76b2fa202760bb7127ce994598bb8d5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2f46184c93f39e820d0dd19186ca1af3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdecap__hw_8h.html#a2f46184c93f39e820d0dd19186ca1af3">XDecap_WriteReg</a>(BaseAddress,  RegOffset,  Data)&#160;&#160;&#160;<a class="el" href="xdecap__hw_8h.html#a351361dd041772e13059c23711f9bf8c">XDecap_Out32</a>((BaseAddress) + ((u32)RegOffset), (u32)(Data))</td></tr>
<tr class="memdesc:a2f46184c93f39e820d0dd19186ca1af3"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro writes a value to a Decap register.  <a href="#a2f46184c93f39e820d0dd19186ca1af3">More...</a><br /></td></tr>
<tr class="separator:a2f46184c93f39e820d0dd19186ca1af3"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
<a id="ab90ba5ed847113b4cdfa527ae8f9d22a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ab90ba5ed847113b4cdfa527ae8f9d22a">&#9670;&nbsp;</a></span>XDecap_HW_H_</h2>

<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XDecap_HW_H_</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Prevent circular inclusions by using protection macros. </p>

</div>
</div>
<a id="a03b582a71ef5398000b744c91fe4890f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a03b582a71ef5398000b744c91fe4890f">&#9670;&nbsp;</a></span>XDecap_In32</h2>

<div class="memitem">
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          <td class="memname">#define XDecap_In32&#160;&#160;&#160;Xil_In32</td>
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<p>Input Operations. </p>

</div>
</div>
<a id="a351361dd041772e13059c23711f9bf8c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a351361dd041772e13059c23711f9bf8c">&#9670;&nbsp;</a></span>XDecap_Out32</h2>

<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XDecap_Out32&#160;&#160;&#160;Xil_Out32</td>
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<p>Output Operations. </p>

</div>
</div>
<a id="aa76b2fa202760bb7127ce994598bb8d5"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aa76b2fa202760bb7127ce994598bb8d5">&#9670;&nbsp;</a></span>XDecap_ReadReg</h2>

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          <td class="memname">#define XDecap_ReadReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;<a class="el" href="xdecap__hw_8h.html#a03b582a71ef5398000b744c91fe4890f">XDecap_In32</a>((BaseAddress) + ((u32)RegOffset))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This macro reads a value from a Decap register. </p>
<p>A 32 bit read is performed. If the component is implemented in a smaller width, only the least significant data is read from the register. The most significant data will be read as 0.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the Decap core instance. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset of the register (defined at the top of this file).</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The 32-bit value of the register.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="xdecap__hw_8h.html#aa76b2fa202760bb7127ce994598bb8d5" title="This macro reads a value from a Decap register. ">XDecap_ReadReg(u32 BaseAddress, u32 RegOffset)</a> </dd></dl>

<p class="reference">Referenced by <a class="el" href="xdecap_8h.html#a496df344c9ce70164599caf0492a7233">XDecap_ChannelClearStatistic()</a>, <a class="el" href="xdecap_8h.html#a49bc056883df1a818d65b26d995ffc40">XDecap_ChannelUpdate()</a>, <a class="el" href="xdecap_8h.html#a4d939d037cae3b5d8926d152cab7ba83">XDecap_ChStatus()</a>, <a class="el" href="xdecap_8h.html#acb7f635ca4ca6e93c3519f140102107e">XDecap_ControlChannelEn()</a>, <a class="el" href="xdecap_8h.html#ae080ecfbaf86030ba14d9953ab84712b">XDecap_ControlMPktDetEn()</a>, <a class="el" href="xdecap_8h.html#a8e303e2c626dbe24800a3cf101f7a4b5">XDecap_ControlMPktDropEn()</a>, <a class="el" href="xdecap_8h.html#a6d58be72ac7fa018f18d54611fe3d641">XDecap_CoreInfo()</a>, <a class="el" href="xdecap_8h.html#a6756049f4dec640fa09ec11cbcd884ce">XDecap_DisablePacketStopIntr()</a>, <a class="el" href="xdecap_8h.html#a0cc9dcb164fba41c5da249cdf32b3817">XDecap_DisableVideoLockIntr()</a>, <a class="el" href="xdecap_8h.html#a4c78c318855982be71fc639e69b828f8">XDecap_DisableVideoUnLockIntr()</a>, <a class="el" href="xdecap_8h.html#ae7d5ad7d53da1ccb16c807ea02052a52">XDecap_DropPcktCnt()</a>, <a class="el" href="xdecap_8h.html#af58cf0b92153c236fd4277e85b8a4d20">XDecap_EnablePacketStopIntr()</a>, <a class="el" href="xdecap_8h.html#ab9203499da148ecf6d80a03bf4900c71">XDecap_EnableVideoLockIntr()</a>, <a class="el" href="xdecap_8h.html#a5d8e8d73c8324347dd85168fb29e0113">XDecap_EnableVideoUnLockIntr()</a>, <a class="el" href="xdecap_8h.html#a615c353c63712fb5b1e2f068526a906a">XDecap_ErrorPacketsCnt()</a>, <a class="el" href="xdecap_8h.html#a72fee94b00405e8fb5545fa3c5a8303a">XDecap_FECValidPcktCnt()</a>, <a class="el" href="xdecap_8h.html#a7ce70a699783f1daf42021d1b72b4aac">XDecap_MatchUDPDest()</a>, <a class="el" href="xdecap_8h.html#aa7aee64a35a170585e54f25b3f303841">XDecap_MatchUDPSrc()</a>, <a class="el" href="xdecap_8h.html#a61f2d8f16b25eb00dc5e7cd5e1c53990">XDecap_MatchVLANID()</a>, <a class="el" href="xdecap_8h.html#ab3422db4c38fed45bdae6b0f631d7eee">XDecap_MediaValidPcktCnt()</a>, <a class="el" href="xdecap_8c.html#ad8355f9c4c5843567f12a31e40b18d69">XDecap_MisMatchedPacketsCnt()</a>, <a class="el" href="xdecap_8h.html#ab670ee51c6189ef9244822f47241b713">XDecap_MismatchPacketCnt()</a>, <a class="el" href="xdecap_8h.html#a18ba8fab593c8fd70338f0b990a868e6">XDecap_ModuleEn()</a>, <a class="el" href="xdecap_8h.html#a2bf262248c92cce79666e89314708605">XDecap_PacketLockWindow()</a>, <a class="el" href="xdecap_8h.html#a4c6be9dde19f85b99084c74a50bc07ad">XDecap_PacketUnLockWindow()</a>, <a class="el" href="xdecap_8h.html#aad8cd81746f674f979c29831a9133f84">XDecap_PeakBufferLv()</a>, <a class="el" href="xdecap_8h.html#a3bc6d719b4635154461ab06fa56ec120">XDecap_ReOrderedPcktCnt()</a>, <a class="el" href="xdecap_8h.html#a666e90cf02f8e2b2273e241abe76585a">XDecap_RXPacketsCnt()</a>, <a class="el" href="xdecap_8h.html#a43e58ca2c814f6340c95cf9e025dfa89">XDecap_SDIPacketLockStatus()</a>, <a class="el" href="xdecap_8h.html#ab25f00adc63140943864c530864dec09">XDecap_SetMatchSelect()</a>, <a class="el" href="xdecap_8h.html#af5c6749868419901a663259817f60991">XDecap_SetOperationMode()</a>, <a class="el" href="xdecap_8h.html#a3703c286e5988ba8c6a8f5f78ca4392d">XDecap_SoftReset()</a>, <a class="el" href="xdecap_8h.html#a8d1b1fb9baadf9abfbdb4ae381988b32">XDecap_StreamStat()</a>, <a class="el" href="xdecap_8h.html#a0ede6ffbec4252136ba2cf552c238a0b">XDecap_StreamStopIntrStatus()</a>, <a class="el" href="xdecap_8h.html#aa0d6c2a9bbd75692d371f561398ad505">XDecap_ToMatchVLANID()</a>, <a class="el" href="xdecap_8h.html#a698a7e99a597a4793a2dda468ec8c0b2">XDecap_VideoLockIntrStatus()</a>, and <a class="el" href="xdecap_8h.html#a0034eb23294b119ac39dd5960ca01110">XDecap_VideoUnLockIntrStatus()</a>.</p>

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<a id="a2f46184c93f39e820d0dd19186ca1af3"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a2f46184c93f39e820d0dd19186ca1af3">&#9670;&nbsp;</a></span>XDecap_WriteReg</h2>

<div class="memitem">
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        <tr>
          <td class="memname">#define XDecap_WriteReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;<a class="el" href="xdecap__hw_8h.html#a351361dd041772e13059c23711f9bf8c">XDecap_Out32</a>((BaseAddress) + ((u32)RegOffset), (u32)(Data))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This macro writes a value to a Decap register. </p>
<p>A 32 bit write is performed. If the component is implemented in a smaller width, only the least significant data is written.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the Decap core instance. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset of the register (defined at the top of this file) to be written. </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit value to write into the register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xdecap__hw_8h.html#a2f46184c93f39e820d0dd19186ca1af3" title="This macro writes a value to a Decap register. ">XDecap_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)</a> </dd></dl>

<p class="reference">Referenced by <a class="el" href="xdecap_8h.html#a974568f7baaf370736865b67e04d82b6">XDecap_ChannelAccess()</a>, <a class="el" href="xdecap_8h.html#aab7cf05a65917b6110255eb6ce7afeba">XDecap_ClearGeneralStatistic()</a>, <a class="el" href="xdecap_8h.html#ab30b274c583239acf948997ed004d891">XDecap_IntrClear()</a>, <a class="el" href="xdecap_8h.html#ab5009a5a4677df3265536c2eabccede6">XDecap_MatchIPv4Dest()</a>, <a class="el" href="xdecap_8h.html#afff0cbc7c218ded47ca987b4ac700ad1">XDecap_MatchIPv4Src()</a>, <a class="el" href="xdecap_8h.html#a6f0111c3756e356a0b4cbc56b938cce5">XDecap_MatchSSRC()</a>, and <a class="el" href="xdecap_8h.html#ac2a1ed398e315e4c0a0c827fe6282e6e">XDecap_PacketStopTimer()</a>.</p>

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